1. Field of the Invention
The present invention relates to a memory device using a semiconductor.
2. Description of the Related Art
A static random access memory (an SRAM) using two inverters for its memory cell operates at high speed, and thus is used to temporarily store programs and/or data either in the CPU or in a part near the CPU. Unlike a dynamic random access memory (a DRAM), the SRAM does not require to be refreshed while storing data, thereby consuming less power in standby mode. For this reason, the SRAM is also used for data storage in a portable device.
FIG. 2A illustrates a conventional SRAM memory cell. The memory cell is connected to two bit lines BL1 and BL2 and one word line WL. The memory cell includes two selection transistors STr1 and STr2 and two inverters INV1 and INV2. The gates of the selection transistors STr1 and STr2 are connected to the word line WL. The drain of the selection transistor STr1 is connected to the bit line BL1, and the drain of the selection transistor STr2 is connected to the bit line BL2.
The source of the selection transistor STr1 is connected to the output of the INV1 and the input of the INV2. The source of the selection transistor STr2 is connected to the output of the INV2 and the input of the INV1. In other words, the output of the inverter INV1 is connected to the input of the inverter INV2, and the output of the inverter INV2 is connected to the input of the inverter INV1. A circuit in which two inverters are connected to each other in this way is called a flip-flop circuit.
Complementary inverters are used as these inverters to achieve low power consumption. In a complementary inverter, the gate of the p-type transistor and the gate of the n-type transistor are connected to each other, serving as the input of the inverter. Moreover, the drain of the p-type transistor and the drain of the n-type transistor are connected to each other, serving as the output of the inverter. Further, the potential of the source of the p-type transistor (the positive electrode of the inverter) is held high (VDD), and the potential of the source of the n-type transistor (the negative electrode of the inverter) is held low (VSS).
The normal characteristics of the complementary inverter are illustrated in FIG. 2B. Here, the threshold voltage of the n-type transistor is denoted by Vth_N, and the threshold voltage of the p-type transistor is denoted as Vth_P. If input potential VIN is between VSS and (VSS+Vth_N), output potential VOUT becomes potential VDD. If input potential VIN is between (VDD−|Vth_P|) and VDD, output potential VOUT becomes potential VSS.
If input potential VIN is between (VSS+Vth_N) and (VDD−|Vth_P|), both the p-type transistor and the n-type transistor are on, and output potential VOUT is determined by the resistance ratio therebetween. Since both the p-type transistor and the n-type transistor are on, relatively high current called flow-through current flows between the positive and negative electrodes of the inverter.
In order to write data into the SRAM memory cell, an appropriate potential is applied to the word line WL to turn on the selection transistors STr1 and STr2 and, while the selection transistors STr1 and STr2 are on, potentials according to the data are applied to the bit lines BL1 and BL2, where the phase of the potentials are opposite each other. For example, potential VDD is applied to the bit line BL1, and potential VSS is applied to the bit line BL2.
Consequently, the output of the inverter INV1 becomes potential VSS, and the output of the inverter INV2 becomes potential VDD. Each of these outputs has the same potential as the bit line connected to the output of the inverter through the selection transistor (STr1 or STr2). This potential is input to the other inverter. Thus, the flip-flop circuit goes into a stable state.
In order to read data, an appropriate potential is applied to the word line WL to turn on the selection transistors STr1 and STr2 and, while these transistors are on, changes in the potentials of the bit lines are monitored. Here, if the on-resistances of the selection transistors STr1 and STr2 are too low, the output potentials of the inverters are affected by the potential of the bit line, so that the flip-flop circuit becomes unstable, which may results in loss of data.
Therefore, the following measures are taken to avoid instability: the potentials of the bit lines are set between VDD and VSS in advance to turn on the selection transistors STr1 and STr2; and/or the on-resistances of the selection transistors STr1 and STr2 are set approximately equal to or higher than or equal to the on-resistances of the transistors forming the inverters.
By the way, in resent years, a reduction in the difference between potential VDD and potential VSS (lower voltage operation) is required to further reduce power consumption. The inverter characteristics shown in FIG. 2B are those obtained when VDD−VSS>Vth_N+|Vth_P|, whereas the inverter characteristics shown by the solid line in FIG. 2C are those obtained when lower voltage operation is achieved, so that VDD−VSS<Vth_N+|Vth_P|.
Here, if input potential VIN is between VSS and (VDD−|Vth_P|), output potential VOUT becomes potential VDD. If input potential VIN is between (VSS+Vth_N) and VDD, output potential VOUT becomes potential VSS.
If input potential VIN is between (VDD−|Vth_P|) and (VSS+Vth_N), both of the p-type and n-type transistors are off, and output potential VOUT is determined by the resistance ratio therebetween. However, since both of them have high resistance, output potential VOUT in this region is extremely unstable and fails to respond in short time.
For example, even if input potential VIN is apparently slightly higher than (VDD−|Vth_P|), output potential VOUT is almost VDD. This is because the resistance of the p-type transistor is relatively lower than that of the n-type transistor, and both of the transistors are in the subthreshold states. In other words, the resistance of the p-type transistor here is several to dozens of times that obtained when input potential VIN is (VDD−|Vth_P|). Therefore, when a load is connected to the output of the inverter, output potential of the inverter may drastically change regardless of the input of the inverter.
For this reason, input potential VIN that produces a stable output of VDD or VSS is limited to the range from VSS to (VDD−|Vth_P|) and the range from (VSS+Vth_N) to VDD. For example, each of these ranges has a width of only 0.2 V in the case where VDD=+0.8 V, VSS=0 V, Vth_P=−0.6 V, and Vth_N=+0.6 V. In contrast, in the case shown in FIG. 2B, since VDD−VSS=1.6 V, each of the ranges has a width of as large as 0.6 V in which output potential VOUT becomes VDD or VSS.
In addition, as a result of the miniaturization of the transistors, statistical fluctuations of impurity concentrations in the channels have became nonnegligible, which poses the problems of threshold voltage variations among the transistors (Non-Patent Document 1). Consequently, characteristics variations among inverters using transistors with a channel length of 0.1 μm or less have been increased. This has further narrowed the range of actually available input potential VIN.
For example, if Vth_P=−0.7 V and Vth_N=+0.7 V, input potential VIN that can be used in a stable state is in the range from 0 V to +0.1 V and in the range from +0.7 V to +0.8 V each of which has a width of only 0.1 V.
If Vth_P=−0.7 V and Vth_N=+0.5 V, input potential VIN that can be used in a stable state is in the range from 0 V to +0.1 V and the range from +0.5 V to +0.8 V which provide a width of 0.4 V in total. However, the ranges have different permissible widths; hence, in the flip-flop circuit using the output of one inverter as the input of the other inverter, substantially permissible input potential VIN is in the range from 0 V to +0.1 V and the range from +0.7 V to +0.8 V each of which has a width of 0.1 V.
The characteristics shown in FIGS. 2B and 2C are those in a steady state; the range of actually available input potential VIN is further narrowed when used for a short period, e.g., that for write or read operation in the memory.
Moreover, the lower voltage operation poses the problem of decreasing the writing or reading speed caused by the increase of on-resistance of the on-state transistor included in the inverter. In order to avoid these problems, a method, for example, of controlling the potential of the power sources for the inverter has been proposed (see Patent Document, 1 for example). In this method, the potential of the power sources for the inverter is changed in accordance with data during the write operation.
In the data retention state, the amount of current flowing through the inverter (current flowing from the positive electrode of the inverter to the negative electrode of the inverter) is determined by the resistance of the transistor in the off-state. In this state, a transistor with a normal threshold voltage has an off-resistance of 1×1013Ω, or more. Hence, the leakage current of one inverter is 1×10−13 A or less. For example, one gigabit memory has as many as two billion or more inverters, resulting in consumption of current of as much as 2×10−4 A.
If threshold voltage variations increase as described above as a result of the miniaturization, the number of the transistors having low off-resistances among those forming the inverters increases. A drop of 0.1 V in threshold voltage reduces the off-resistance by a factor of about 30 and increases the leakage current by a factor of about 30. In addition, short-channel effect raises the subthreshold value of the transistors, which may reduce the off-resistance.
Reducing gate insulator thickness can reduce short channel effect or statistical variations in impurity concentration; however, an excessive reduction in gate insulator thickness may increase leakage current between the gate and the channel.
In other words, a highly integrated SRAM has a higher leakage current per one bit than the conventional one, and high integration causes the SRAM in which one chip has a greater number of memory cells to have a higher leakage current for the data retention. However, no effective method has been proposed to reduce such leakage current of the data retention period.